The Basics Introduction to Partial Reconfiguration | Achronix Trainings

This introductory overview of the Achronix Partial Reconfiguration (PR) flow showcases the advantage of our architecture utilizing the 2D NoC to easily replace, move or scale IP blocks throughout the FPGA fabric without the need to recompile or power down the rest of the FPGA. Our Director of Product Marketing, Bill Jenkins, walks you through the procedure to create multiple PR bitstreams by creating keep-out zones, compiling the different RTL that will reside in those zones to create a bitstream, creating a top-level bitstream that will incorporate each of the IP blocks in an overall FPGA design, and finally how to dynamically program and swap each of the IP blocks during runtime. This introduction to Partial Reconfiguration will be a good precursor to a reference design that ships with our latest ACE software and that you can use to start your own design with.

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